The design and implementation of DCT/IDCT chip with novel architecture
نویسندگان
چکیده
In the paper: an efficient VLSI architecture for a 8x 8 twodimensional discrete cosine transform and inverse discrete cosine transform (2-D DCTIIDCT) with a new 1-D DCTIIDCT algorithm is presented. The proposed new algorithm makes all coeficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm [ I ] . For computing 2-D DCTIIDCT: the row-column decomposition method is used, and the design of I-D DCTilDCT requires only 9 multipliers and 2 1 addersisubtractors. This chip is synthesized with 0.6 ,U m standard cell library and 1P3M CMOS technology, and it can be operate up to 100MHz.
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